


#device=PIC16C505

vpp (range=12.750-13.250 dflt=13.000)
vdd (range=2.500-5.500 dfltrange=3.000-5.500 nominal=5.000)

pgming (memtech=eprom ovrpgm=11 tries=8)
    wait (pgm=100 cfg=100 userid=100)

pgmmem (region=0x00-0x3FF)
cfgmem (region=0xFFF-0xFFF)
calmem (region=0x3FF-0x3FF)
testmem (region=0x400-0x43F)
userid (region=0x400-0x403)


NumBanks=4
MirrorRegs (0x00-0x0f  0x20-0x2f  0x40-0x4f  0x60-0x6f)

sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PCL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=STATUS addr=0x3 size=1 access='rw rw rw r r rw rw rw')
    reset (por='00011xxx' mclr='q00qquuu')
    bit (names='RBWUF - PA0 nTO nPD Z DC C')
sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='110xxxxx' mclr='11uuuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=OSCCAL addr=0x5 size=1 access='rw rw rw rw rw rw u u')
    reset (por='100000--' mclr='uuuuuu--')
    bit (names='CAL - -' width='6 1 1')
sfr (key=PORTB addr=0x6 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RB5 RB4 RB3 RB2 RB1 RB0')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=PORTC addr=0x7 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RC5 RC4 RC3 RC2 RC1 RC0')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)



                               # -------------------#
#------------------------------# Configuration Bits #------------------------------------#
                               # -------------------#

cfgbits (key=CONFIG addr=0xFFF unused=0x0)
    field (key=OSC mask=0x7 desc="Oscillator")
        setting (req=0x7 value=0x7 desc="External RC Clockout")
        setting (req=0x7 value=0x6 desc="External RC No Clock")
        setting (req=0x7 value=0x5 desc="Internal RC Clockout")
        setting (req=0x7 value=0x4 desc="Internal RC No Clock")
        setting (req=0x7 value=0x2 desc="HS")
        setting (req=0x7 value=0x1 desc="XT")
        setting (req=0x7 value=0x0 desc="LP")
    field (key=WDT mask=0x8 desc="Watchdog Timer")
        setting (req=0x8 value=0x8 desc="On")
        setting (req=0x8 value=0x0 desc="Off")
    field (key=MCLRE mask=0x20 desc="Master Clear Enable")
        setting (req=0x20 value=0x20 desc="External")
        setting (req=0x20 value=0x0 desc="Internal")
    field (key=CP mask=0xFD0 desc="Code Protect")
        setting (req=0xFD0 value=0xFD0 desc="Off")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0xFD0 value=0x0 desc="On")
            checksum (type=0x20 protregion=0x40-0x3FE)

                               # ---------------------------#
#------------------------------# Nonmemory-Mapped Registers #------------------------------------#
                               # ---------------------------#

nmmr (key=WREG addr=0x0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='qqqqqqqq' mclr='qqqqqqqq')
    bit (names='WREG' width='8')
nmmr (key=STKPTR addr=0x1 size=1 flags=h access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='STKPTR' width='8')
#  Note that this part has no TRISA
nmmr (key=TRISB addr=0x3 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0')
nmmr (key=TRISC addr=0x4 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0')
nmmr (key=OPTION_REG addr=0x5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRBWU nRBPU T0CS T0SE PSA PS' width='1 1 1 1 1 3')


                               # ------------#
#------------------------------# Peripherals #------------------------------------#
                               # ------------#
#--------------------------------------------------------------------------------
# 				PORTB
#--------------------------------------------------------------------------------
peripheral (key=PORTB sfrs='TRISB PORTB' type=port)
    iopin (key=RB0 dir=inout)
        cnpin (key=GPIO0CN notify=CORE)
    iopin (key=RB1 dir=inout)
        cnpin (key=GPIO1CN notify=CORE)
    iopin (key=RB2 dir=inout)
    iopin (key=RB3 dir=inout)
        cnpin (key=GPIO3CN notify=CORE)
    iopin (key=RB4 dir=inout)
        cnpin (key=GPIO4CN notify=CORE)
    iopin (key=RB5 dir=inout)


#--------------------------------------------------------------------------------
# 				PORTC
#--------------------------------------------------------------------------------

peripheral (key=PORTC sfrs='TRISC PORTC' type=port)
    iopin (key=RC0 dir=inout)
    iopin (key=RC1 dir=inout)
    iopin (key=RC2 dir=inout)
    iopin (key=RC3 dir=inout)
    iopin (key=RC4 dir=inout)
    iopin (key=RC5 dir=inout)

#--------------------------------------------------------------------------------
# 				TIMERs
#--------------------------------------------------------------------------------
peripheral (key=TMR0 sfrs='TMR0')
    pinfunc (key=T0CKI port=RC5 dir=in)

#--------------------------------------------------------------------------------
# 				OSC
#--------------------------------------------------------------------------------

peripheral (key=OSC)
    pinfunc (key=OSC1 port=RB5 dir=out)
    pinfunc (key=OSC2 port=RB4 dir=in)

#--------------------------------------------------------------------------------
# 				MCLR
#--------------------------------------------------------------------------------
peripheral (key=MCLR)
    pinfunc (key=MCLR port=RB3 dir=in)

