
format=0.1

#device=PIC18F2450
# DOS: DOS-00656
# PS:  DS-XXXXX
# DS:  DS-XXXXX

vpp (range=9.500-12.500 dflt=12.000)
vdd (range=2.125-5.500 dfltrange=4.250-5.500 nominal=5.000)

# Single Panel Programming 
pgming (memtech=ee tries=1 lvpthresh=3.000 panelsize=0x0) 
    wait (pgm=1000 lvpgm=1000 eedata=4000 cfg=5000 userid=5000 erase=10000 lverase=1000)
    latches(pgm=8 eedata=2 userid=8 cfg=2 rowerase=64)   	# Latches are the number of bytes

pgmmem (region=0x0-0x3FFF)
cfgmem (region=0x300000-0x30000D)
calmem (region=0x300100-0x300204)
testmem (region=0x200000-0x20003F)
userid (region=0x200000-0x200007)

# The end address has been changed from a 0x2B to a 0x37 for the ICD2
bkbgvectmem (region=0x200028-0x200037)
devid (region=0x3FFFFE-0x3FFFFF idmask=0xFFE0 id=0x2420)

UnusedBankMask=0x7FEC
AccessBankSplitOffset=0x80
NumBanks=16

# Check these values before relying upon them.
UnusedRegs (0xf00-0xf5F)
UnusedRegs (0xf83-0xf88)
UnusedRegs (0xf8c-0xf91)
UnusedRegs (0xf95-0xf9c)
UnusedRegs (0xfa3-0xfa5)
UnusedRegs (0xfa8-0xfaa)
UnusedRegs (0xfb0-0xfb5)
UnusedRegs (0xfb8-0xfb9)
UnusedRegs (0xfc9-0xfc5)
UnusedRegs (0xfd4-0xfd4)


                               # ---------------#
#------------------------------# CORE Registers #------------------------------------------------#
                               # ---------------#

sfr (key=TOS addr=0xFFD size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - TOS' width='1 1 1 21')
sfr (key=TOSU addr=0xFFF size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - TOSU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TOSH addr=0xFFE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TOSL addr=0xFFD size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=STKPTR addr=0xFFC size=1 access='rc rc u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='STKFUL STKUNF - STKPTR' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=PCLAT addr=0xFF9 size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - PCLAT' width='1 1 1 21')
sfr (key=PCLATU addr=0xFFB size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PCLATH addr=0xFFA size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PCL addr=0xFF9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=TBLPTR addr=0xFF6 size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - ACSS TBLPTR' width='1 1 1 21')
sfr (key=TBLPTRU addr=0xFF8 size=1 access='u u rw rw rw rw rw rw')
    # NOTE: The ACSS bit allows access to the device configuration bits
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACSS TBLPTRU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TBLPTRH addr=0xFF7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TBLPTRL addr=0xFF6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=TABLAT addr=0xFF5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TABLAT' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=PROD addr=0xFF3 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='PROD' width='16')
sfr (key=PRODH addr=0xFF4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PRODL addr=0xFF3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=INTCON addr=0xFF2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='0000000x' mclr='0000000u')
    bit (names='GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    # NOTE: When IPEN (bit 7) in the RCON register is 0 use the following bit names
    qbit (names='GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    # NOTE: When IPEN (bit 7) in the RCON register is 1 use the following bit names
    qbit (names='GIEH GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    bit (tag=scl names='GIE_GIEH PEIE_GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
# Q: I changed the name of b7 from '-' to 'nRBPU' upon discovering the
# name in DOS C.  Unfortunately, I don't have reset or access info on
# this bit and these values are certainly incorrect.
sfr (key=INTCON2 addr=0xFF1 size=1 access='u rw rw rw u rw u rw')
    reset (por='-111-1-1' mclr='-111-1-1')
    bit (names='nRBPU INTEDG0 INTEDG1 INTEDG2 - TMR0IP - RBIP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=INTCON3 addr=0xFF0 size=1 access='rw rw u rw rw u rw rw')
    reset (por='11-00-00' mclr='11-00-00')
    bit (names='INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=INDF0 addr=0xFEF size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF0' width='8')
sfr (key=POSTINC0 addr=0xFEE size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC0' width='8')
sfr (key=POSTDEC0 addr=0xFED size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC0' width='8')
sfr (key=PREINC0 addr=0xFEC size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC0' width='8')
sfr (key=PLUSW0 addr=0xFEB size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW0' width='8')

# Q: I'm curious as to why the 'por' reset state for the implemented
# bits in FSR0H and FSR0L are different.  This may be an error.  Keep
# in mind that these values were copied from another device file, so
# they are probably incorrect there as well.
sfr (key=FSR0 addr=0xFE9 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR0' width='1 1 1 1 12')
sfr (key=FSR0H addr=0xFEA size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR0H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR0L addr=0xFE9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR0L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=WREG addr=0xFE8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='WREG' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=rw)
sfr (key=INDF1 addr=0xFE7 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF1' width='8')
sfr (key=POSTINC1 addr=0xFE6 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC1' width='8')
sfr (key=POSTDEC1 addr=0xFE5 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC1' width='8')
sfr (key=PREINC1 addr=0xFE4 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC1' width='8')
sfr (key=PLUSW1 addr=0xFE3 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW1' width='8')

# Q: See note on FSR0.
sfr (key=FSR1 addr=0xFE1 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR1' width='1 1 1 1 12')
sfr (key=FSR1H addr=0xFE2 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR1H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR1L addr=0xFE1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR1L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=BSR addr=0xFE0 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - BSR' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=INDF2 addr=0xFDF size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF2' width='8')
sfr (key=POSTINC2 addr=0xFDE size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC2' width='8')
sfr (key=POSTDEC2 addr=0xFDD size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC2' width='8')
sfr (key=PREINC2 addr=0xFDC size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC2' width='8')
sfr (key=PLUSW2 addr=0xFDB size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW2' width='8')

# Q: See not on FSR0.
sfr (key=FSR2 addr=0xFD9 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR2' width='1 1 1 1 12')
sfr (key=FSR2H addr=0xFDA size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - FSR2H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR2L addr=0xFD9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR2L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=STATUS addr=0xFD8 size=1 access='u u u rw rw rw rw rw')
    reset (por='---xxxxx' mclr='---uuuuu')
    bit (names='- - - N OV Z DC C')

sfr (key=LVDCON addr=0xFD2 size=1 access='u u r rw rw rw rw rw')
    reset (por='--000101' mclr='--000101')
    bit (names='- - IRVST LVDEN LVDL' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=WDTCON addr=0xFD1 size=1 access='u u u u u u u rw')
    reset (por='-------0' mclr='-------0')
    bit (names='- - - - - - - SWDTEN')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=RCON addr=0xFD0 size=1 access='rw rw u rw rw rw rw rw')
    reset (por='01-11100' mclr='01-uqquu')
    bit (names='IPEN SBOREN - nRI nTO nPD nPOR nBOR')
    stimulus (scl=r regfiles=w pcfiles=rw)

sfr (key=IPR2 addr=0xFA2 size=1 access='rw u rw u u rw u u')
    reset (por='1-1--1--' mclr='1-1--1--')
    bit (names='OSCFIP - USBIP - - LVDIP - -')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR2 addr=0xFA1 size=1 access='rw u rw u u rw u u')
    reset (por='0-0--0--' mclr='0-0--0--')
    bit (names='OSCFIF - USBIF - - LVDIF - -')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIE2 addr=0xFA0 size=1 access='rw u rw u u rw u u')
    reset (por='0-0--0--' mclr='0-0--0--')
    bit (names='OSCFIE - USBIE - - LVDIE - -')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=IPR1 addr=0xF9F size=1 access='u rw rw rw u rw rw rw')
    reset (por='-111-111' mclr='-111-111')
    bit (names='- ADIP RCIP TXIP - CCP1IP TMR2IP TMR1IP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR1 addr=0xF9E size=1 access='u rw r r u rw rw rw')
    reset (por='-000-000' mclr='-000-000')
    bit (names='- ADIF RCIF TXIF - CCP1IF TMR2IF TMR1IF')
    bit (tag=scl names='- ADIF - - - CCP1IF TMR2IF TMR1IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIE1 addr=0xF9D size=1 access='u rw rw rw u rw rw rw')
    reset (por='-000-000' mclr='-000-000')
    bit (names='- ADIE RCIE TXIE - CCP1IE TMR2IE TMR1IE')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # ---------------------#
#------------------------------# Oscillator Registers #----------------------------------------------------------------------------#
                               # ---------------------#

# Q: The access flags and reset values do not appear correct, yet I
# have no data on them.
sfr (key=OSCCON addr=0xFD3 size=1 access='u rw rw rw u r u u')
    reset (por='-000-0--' mclr='-000-0--')
    bit (names='IDLEN - OSTS FLTS SCS' width='1 3 1 1 2')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # ----------------#
#------------------------------# PORTA Registers #-------------------------------------------------#
                               # ----------------#

# RA6/RA7 and associated bits are individually configured as port pins based on various primary 
# oscillator modes.  When disabled, the bits read '0'.

sfr (key=PORTA addr=0xF80 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xx0x0000' mclr='uu0u0000')
    bit (names='RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATA addr=0xF89 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0')
    bit (tag=scl names='LATA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISA addr=0xF92 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTB Registers #-----------------------------------------------------------------------------------------#
                               # ----------------#

sfr (key=PORTB addr=0xF81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=TRISB addr=0xF93 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0')
    bit (tag=scl names='TRISB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATB addr=0xF8A size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0')
    bit (tag=scl names='LATB' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTC Registers #---------------------------------------#
                               # ----------------#

sfr (key=PORTC addr=0xF82 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATC addr=0xF8B size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0')
    bit (tag=scl names='LATC' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISC addr=0xF94 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# ADC Registers #----------------------------------------------------------------------------#
                               # --------------#

sfr (key=ADRES addr=0xFC3 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='ADRES' width='16')
sfr (key=ADRESH addr=0xFC4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESH' width='8')
    stimulus (scl=rwb type=int)
sfr (key=ADRESL addr=0xFC3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESL' width='8')
    stimulus (scl=rwb type=int regfiles=r)

sfr (key=ADCON0 addr=0xFC2 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - CHS GO/nDONE ADON' width='1 1 4 1 1')
    bit (tag=scl names='- - CHS GO_nDONE ADON' width='1 1 4 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON1 addr=0xFC1 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--00qqqq' mclr='--000000')
    bit (names='- - VCFG PCFG' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON2 addr=0xFC0 size=1 access='rw u rw rw rw rw rw rw')
    reset (por='0-000000' mclr='0-000000')
    bit (names='ADFM - ACQT ADCS' width='1 1 3 3')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# CCP Registers #----------------------------------------------------------------------------#
                               # --------------#

sfr (key=CCPR1 addr=0xFBE size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='CCPR1' width='16')
sfr (key=CCPR1H addr=0xFBF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=CCPR1L addr=0xFBE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb type=int regfiles=w)

sfr (key=CCP1CON addr=0xFBD size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='P1M DC1B CCP1M' width='2 2 4')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER0 Registers #-------------------------------------------------#
                               # -----------------#

# Q: Here is yet another case where the reset states of bits differ in
# the high byte and low byte!  I smell an error.
sfr (key=TMR0 addr=0xFD6 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='TMR0' width='16')
sfr (key=TMR0H addr=0xFD7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR0H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR0L addr=0xFD6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)

sfr (key=T0CON addr=0xFD5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TMR0ON T08BIT T0CS T0SE T0PS' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER1 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=TMR1 addr=0xFCE size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='TMR1' width='16')
sfr (key=TMR1H addr=0xFCF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR1L addr=0xFCE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)

sfr (key=T1CON addr=0xFCD size=1 access='rw r rw rw rw rw rw rw')
    reset (por='00000000' mclr='u0uuuuuu')
    bit (names='RD16 T1RUN T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER2 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=TMR2 addr=0xFCC size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=PR2 addr=0xFCB size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=T2CON addr=0xFCA size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- TOUTPS TMR2ON T2CKPS' width='1 4 1 2')
    stimulus (scl=rwb regfiles=w)

                               # ---------------#
#------------------------------# UART Registers #-------------------------------------------------#
                               # ---------------#

sfr (key=SPBRG addr=0xFAF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCREG addr=0xFAE size=1 access='r r r r r r r r')
    reset (por='00000000' mclr='00000000')
    bit (names='RCREG' width='8')
    stimulus (scl=rb regfiles=rp)
sfr (key=TXREG addr=0xFAD size=1 access='w w w w w w w w')
    reset (por='00000000' mclr='00000000')
    bit (names='TXREG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TXSTA addr=0xFAC size=1 access='rw rw rw rw rw rw r rw')
    reset (por='00000010' mclr='00000010')
    bit (names='CSRC TX9 TXEN SYNC - BRGH TRMT TX9D')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCSTA addr=0xFAB size=1 access='rw rw rw rw rw r r r')
    reset (por='0000000x' mclr='0000000x')
    bit (names='SPEN RX9 SREN CREN ADDEN FERR OERR RX9D')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# EEPROM Registers #----------------------------------------------------------------------------#
                               # -----------------#
sfr (key=EECON2 addr=0xFA7 size=1 flags=w access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')
sfr (key=EECON1 addr=0xFA6 size=1 access='u rw u rw rw rw rs u')
    reset (por='-x-0x00-' mclr='-u-0u00-')
    bit (names='- CFGS - FREE WRERR WREN WR -')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # -------------------#
#------------------------------# Configuration Bits #------------------------------------#
                               # -------------------#

cfgbits (key=CONFIG1L addr=0x300000 unused=0x0)
    field (key=USBPLL mask=0x20 desc="Full-Speed USB Clock Source Selection" init=0)
        setting (req=0x20 value=0x20 desc="Clock src from 96MHz PLL/2")
        setting (req=0x20 value=0x00 desc="Clock src from OSC1/OSC2")
    field (key=CPUDIV mask=0x18 desc="CPU System Clock Postscaler" init=0)
        setting (req=0x18 value=0x18 desc="[OSC1/OSC2 Src: /4][96MHz PLL Src: /6]")
        setting (req=0x18 value=0x10 desc="[OSC1/OSC2 Src: /3][96MHz PLL Src: /4]")
        setting (req=0x18 value=0x08 desc="[OSC1/OSC2 Src: /2][96MHz PLL Src: /3]")
        setting (req=0x18 value=0x00 desc="[OSC1/OSC2 Src: /1][96MHz PLL Src: /2]")
    field (key=PLLDIV mask=0x07 desc="96MHz PLL Prescaler" init=0)
        setting (req=0x07 value=0x07 desc="Divide by 12 (48MHz input)")
        setting (req=0x07 value=0x06 desc="Divide by 10 (40MHz input)")
        setting (req=0x07 value=0x05 desc="Divide by 6 (24MHz input)")
        setting (req=0x07 value=0x04 desc="Divide by 5 (20MHz input)")
        setting (req=0x07 value=0x03 desc="Divide by 4 (16MHz input)")
        setting (req=0x07 value=0x02 desc="Divide by 3 (12MHz input)")
        setting (req=0x07 value=0x01 desc="Divide by 2 (8MHz input)")
        setting (req=0x07 value=0x00 desc="No Divide (4MHz input)")
cfgbits (key=CONFIG1H addr=0x300001 unused=0x0)
	field (key=OSC mask=0xF desc="Oscillator" init=0x5)
        setting (req=0xE value=0xE desc="HS: HS+PLL, USB-HS" freqmin=4000000 freqmax=48000000)
        setting (req=0xE value=0xC desc="HS: USB-HS" freqmin=4000000 freqmax=25000000)
        setting (req=0xF value=0xB desc="INTOSC: USB-HS")
        setting (req=0xF value=0xA desc="INTOSC: USB-XT")
        setting (req=0xF value=0x9 desc="INTOSC: INTOSC+CLK0{RA6}, USB-EC")
        setting (req=0xF value=0x8 desc="INTOSC: INTOSC+RA6, USB-EC")
        setting (req=0xF value=0x7 desc="EC: EC+PLL, EC+PLL+CLKO{RA6}, USB-EC" freqmin=32000 freqmax=48000000)
        setting (req=0xF value=0x6 desc="EC: EC+PLL, EC+PLL+RA6, USB-EC" freqmin=32000 freqmax=48000000)
        setting (req=0xF value=0x5 desc="EC: EC+CLKO{RA6}, USB-EC" freqmin=32000 freqmax=48000000)
        setting (req=0xF value=0x4 desc="EC: EC+RA6, USB-EC" freqmin=32000 freqmax=48000000)
        setting (req=0xE value=0x2 desc="XT: XT+PLL, USB-XT" freqmin=100000 freqmax=4000000)
        setting (req=0xE value=0x0 desc="XT: USB-XT" freqmin=100000 freqmax=4000000)
    field (key=FCMEN mask=0x40 desc="Fail-Safe Clock Monitor Enable" init=0)
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x0 desc="Disabled")
    field (key=IESO mask=0x80 desc="Internal External Switch Over Mode" init=0)
        setting (req=0x80 value=0x80 desc="Enabled")
        setting (req=0x80 value=0x0 desc="Disabled")
        
cfgbits (key=CONFIG2L addr=0x300002 unused=0x0)
    field (key=VREGEN mask=0x20 desc="USB Voltage Regulator" init=0)
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x00 desc="Disabled")
    field (key=PUT mask=0x1 desc="Power Up Timer")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=BODEN mask=0x6 desc="Brown Out Detect")
        setting (req=0x6 value=0x6 desc="Enabled in hardware, SBOREN disabled")
        setting (req=0x6 value=0x4 desc="Enabled while active,disabled in SLEEP,SBOREN disabled")
        setting (req=0x6 value=0x2 desc="Controlled with SBOREN bit")
        setting (req=0x6 value=0x0 desc="Disabled in hardware, SBOREN disabled")
    field (key=BODENV mask=0x18 desc="Brown Out Voltage")
        setting (req=0x18 value=0x18 desc="2.0V")
        setting (req=0x18 value=0x10 desc="2.7V")
        setting (req=0x18 value=0x08 desc="4.2V")
        setting (req=0x18 value=0x00 desc="4.5V")    
        
cfgbits (key=CONFIG2H addr=0x300003 unused=0x0)
    field (key=WDT mask=0x1 desc="Watchdog Timer")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled-Controlled by SWDTEN bit")
    field (key=WDTPS mask=0x1E desc="Watchdog Postscaler")
        setting (req=0x1E value=0x1E desc="1:32768")
        setting (req=0x1E value=0x1C desc="1:16384")
        setting (req=0x1E value=0x1A desc="1:8192")
        setting (req=0x1E value=0x18 desc="1:4096")
        setting (req=0x1E value=0x16 desc="1:2048")
        setting (req=0x1E value=0x14 desc="1:1024")
        setting (req=0x1E value=0x12 desc="1:512")
        setting (req=0x1E value=0x10 desc="1:256")
        setting (req=0x1E value=0x0E desc="1:128")
        setting (req=0x1E value=0x0C desc="1:64")
        setting (req=0x1E value=0x0A desc="1:32")
        setting (req=0x1E value=0x08 desc="1:16")
        setting (req=0x1E value=0x06 desc="1:8")
        setting (req=0x1E value=0x04 desc="1:4")
        setting (req=0x1E value=0x02 desc="1:2")
        setting (req=0x1E value=0x00 desc="1:1")
        
        
cfgbits (key=CONFIG3H addr=0x300005 unused=0x0)
    field (key=PBADEN mask=0x2 desc="PortB A/D Enable")
        setting (req=0x2 value=0x2 desc="PORTB<4:0> configured as analog inputs on RESET")
        setting (req=0x2 value=0x0 desc="PORTB<4:0> configured as digital I/O on RESET")
    field (key=LPT1OSC mask=0x04 desc="Low Power Timer1 Osc enable" init=0)
        setting (req=0x04 value=0x04 desc="Enabled")
        setting (req=0x04 value=0x00 desc="Disabled")
    field (key=MCLRE mask=0x80 desc="Master Clear Enable")
        setting (req=0x80 value=0x80 desc="MCLR Enabled,RE3 Disabled")
        setting (req=0x80 value=0x00 desc="MCLR Disabled,RE3 Enabled")
        
cfgbits (key=CONFIG4L addr=0x300006 unused=0x0)
    field (key=STVR mask=0x1 desc="Stack Overflow Reset")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
    field (key=LVP mask=0x4 desc="Low Voltage Program")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
	field (key=BBSIZ mask=0x8 desc="Boot Block Size Select" init=0)
        setting (req=0x8 value=0x8 desc="2 KW")
            checksum (type=0x27 protregion=0x00-0xFFF)
        setting (req=0x8 value=0x0 desc="1 KW")
            checksum (type=0x27 protregion=0x00-0x7FF)
    field (key=ENICPORT mask=0x20 desc="Dedicated In-Circuit Port {ICD/ICSP}" init=0)
        setting (req=0x20 value=0x20 desc="Enabled")
        setting (req=0x20 value=0x00 desc="Disabled")
    field (key=ENHCPU mask=0x40 desc="Extended CPU Enable" init=0)
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x00 desc="Disabled")
    field (key=BACKBUG mask=0x80 desc="Background Debug" flags=h)
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
        
cfgbits (key=CONFIG5L addr=0x300008 unused=0x0)
    field (key=CP_0 mask=0x1 desc="Code Protect 00800-01FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x1 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x800-0x1FFF)
    field (key=CP_1 mask=0x2 desc="Code Protect 02000-03FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x2 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x2000-0x3FFF)
    # removed per DOS 656 A.1 11-18-2005	
    #field (key=CP_2 mask=0x4 desc="Code Protect 04000-05FFF" flags=xh)
    #    setting (req=0x4 value=0x4 desc="Disabled")
    #        checksum (type=0x0 protregion=0x00-0x00)
    #    setting (req=0x4 value=0x00 desc="Enabled")
    #        checksum (type=0x27 protregion=0x4000-0x5FFF)
    #field (key=CP_3 mask=0x8 desc="Code Protect 06000-07FFF" flags=xh)
    #    setting (req=0x8 value=0x8 desc="Disabled")
    #        checksum (type=0x0 protregion=0x00-0x00)
    #    setting (req=0x8 value=0x00 desc="Enabled")
    #        checksum (type=0x27 protregion=0x6000-0x7FFF)
            
            
cfgbits (key=CONFIG5H addr=0x300009 unused=0x0)
	#Added by Akram on 12th August 2005
#	field (key=CPD mask=0x80 desc="Data EE Read Protect")
#        setting (req=0x80 value=0x80 desc="Disabled")
#        setting (req=0x80 value=0x0 desc="Enabled")
    #Added by Akram on 12th August 2005
    field (key=CPB mask=0x40 desc="Code Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x0-0x7FF)
            
cfgbits (key=CONFIG6L addr=0x30000A unused=0x0)
    field (key=WRT_0 mask=0x1 desc="Table Write Protect 00800-01FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x00 desc="Enabled")
    field (key=WRT_1 mask=0x2 desc="Table Write Protect 02000-03FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x00 desc="Enabled")
    # removed per DOS 656 A.1 11-18-2005	
    #field (key=WRT_2 mask=0x4 desc="Table Write Protect 04000-05FFF" flags=xh)
    #    setting (req=0x4 value=0x4 desc="Disabled")
    #    setting (req=0x4 value=0x00 desc="Enabled")
    #field (key=WRT_3 mask=0x8 desc="Table Write Protect 06000-07FFF" flags=xh)
    #    setting (req=0x8 value=0x8 desc="Disabled")
    #    setting (req=0x8 value=0x00 desc="Enabled")
        
cfgbits (key=CONFIG6H addr=0x30000B unused=0x0)
	#Added by Akram on 12 August 2005                     
#   	field (key=WRTD mask=0x80 desc="Data EEPROM Write Protect")
#        setting (req=0x80 value=0x80 desc="Disabled")
#        setting (req=0x80 value=0x0 desc="Enabled")
    #Added by Akram on 12 August 2005                     
    field (key=WRTC mask=0x20 desc="Config. Write Protect")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
    field (key=WRTB mask=0x40 desc="Table Write Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
        
cfgbits (key=CONFIG7L addr=0x30000C unused=0x0)
    field (key=EBTR_0 mask=0x1 desc="Table Read Protect 00800-01FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x00 desc="Enabled")
    field (key=EBTR_1 mask=0x2 desc="Table Read Protect 02000-03FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x00 desc="Enabled")
    # removed per DOS 656 A.1 11-18-2005	
    #field (key=EBTR_2 mask=0x4 desc="Table Read Protect 04000-05FFF" flags=xh)
    #    setting (req=0x4 value=0x4 desc="Disabled")
    #    setting (req=0x4 value=0x00 desc="Enabled")
    #field (key=EBTR_3 mask=0x8 desc="Table Read Protect 06000-07FFF" flags=xh)
    #    setting (req=0x8 value=0x8 desc="Disabled")
    #    setting (req=0x8 value=0x00 desc="Enabled")       
        
cfgbits (key=CONFIG7H addr=0x30000D unused=0x0)
    field (key=EBTRB mask=0x40 desc="Table Read Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")


                               # ------------#
#------------------------------# Peripherals #------------------------------------#
                               # ------------#

#--------------------------------------------------------------------------------
# 				TIMERs
#--------------------------------------------------------------------------------

peripheral18 (key=TMR0 sfrs='TMR0H TMR0L T0CON')
    pinfunc (key=T0CKI port=RA4 dir=in)
    interrupt (name=TMR0INT enreg=INTCON enmask=0x20 flgreg=INTCON flgmask=0x04 prireg=INTCON2 primask=0x04)

peripheral18 (key=TMR1 sfrs='TMR1H TMR1L T1CON')
    pinfunc (key=T1CKI port=RC0 dir=in)
    interrupt (name=TMR1INT enreg=PIE1 enmask=0x01 flgreg=PIR1 flgmask=0x01 prireg=IPR1 primask=0x01)

peripheral18 (key=TMR2 sfrs='TMR2 PR2 T2CON')
    interrupt (name=TMR2INT enreg=PIE1 enmask=0x02 flgreg=PIR1 flgmask=0x02 prireg=IPR1 primask=0x02)

#--------------------------------------------------------------------------------
# 				ADC
#--------------------------------------------------------------------------------

peripheral18 (key=ADC sfrs='ADCON0 ADCON1 ADCON2 ADRESL ADRESH')
    pinfunc (key=AN0 port=RA0 dir=in)
    pinfunc (key=AN1 port=RA1 dir=in)
    pinfunc (key=AN2 port=RA2 dir=in)
    pinfunc (key=AN3 port=RA3 dir=in)
    pinfunc (key=AN4 port=RA5 dir=in)
#    pinfunc (key=AN5 port=RE0 dir=in)
#    pinfunc (key=AN6 port=RE1 dir=in)
#    pinfunc (key=AN7 port=RE2 dir=in)
    pinfunc (key=AN8 port=RB2 dir=in)
    pinfunc (key=AN9 port=RB3 dir=in)
    pinfunc (key=AN10 port=RB1 dir=in)
    pinfunc (key=AN11 port=RB4 dir=in)
    pinfunc (key=AN12 port=RB0 dir=in)
    access (key=ADCON1 mode=AD_PCFG_HEXSEL_POR)
    access (key=ADCON2 mode=AD_ACQUISITION)
    interrupt (name=ADC enreg=PIE1 enmask=0x40 flgreg=PIR1 flgmask=0x40 prireg=IPR1 primask=0x40)

#--------------------------------------------------------------------------------
# 				UARTs
#--------------------------------------------------------------------------------

peripheral18 (key=UART1 sfrs='SPBRG RCREG TXREG TXSTA RCSTA')
    pinfunc (key=U1RX port=RC7 dir=in)
    pinfunc (key=U1TX port=RC6 dir=out)
    interrupt (name=RXINT1 enreg=PIE1 enmask=0x20 flgreg=PIR1 flgmask=0x20 prireg=IPR1 primask=0x20)
    interrupt (name=TXINT1 enreg=PIE1 enmask=0x10 flgreg=PIR1 flgmask=0x10 prireg=IPR1 primask=0x10)

#--------------------------------------------------------------------------------
# 				PORTA
#--------------------------------------------------------------------------------

peripheral18 (key=PORTA sfrs='TRISA LATA PORTA' type=port)
    iopin (key=RA0 dir=inout)
    iopin (key=RA1 dir=inout)
    iopin (key=RA2 dir=inout)
    iopin (key=RA3 dir=inout)
    iopin (key=RA4 dir=inout)
    iopin (key=RA5 dir=inout)
    iopin (key=RA6 dir=inout)
    iopin (key=RA7 dir=inout)

#--------------------------------------------------------------------------------
# 				PORTB
#--------------------------------------------------------------------------------

peripheral18 (key=PORTB sfrs='TRISB LATB PORTB' type=port)
    iopin (key=RB0 dir=inout)
        extint (key=INT0 enreg=INTCON enmask=0x10 flgreg=INTCON flgmask=0x02 prireg=NONE primask=0x00)
#Not required as FLT0 is also INT0 and CCP uses the INT0 as a Fault line.
#	cnpin (key=PWMFLTA notify=ECCP1)
    iopin (key=RB1 dir=inout)
        extint (key=INT1 enreg=INTCON3 enmask=0x08 flgreg=INTCON3 flgmask=0x01 prireg=INTCON3 primask=0x40)
    iopin (key=RB2 dir=inout)
        extint (key=INT2 enreg=INTCON3 enmask=0x10 flgreg=INTCON3 flgmask=0x02 prireg=INTCON3 primask=0x80)
    iopin (key=RB3 dir=inout)
        cnpin (key=CCP2CN notify=CCP2)
    iopin (key=RB4 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI0)
    iopin (key=RB5 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI1)
    iopin (key=RB6 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI2)
    iopin (key=RB7 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI3)

#--------------------------------------------------------------------------------
# 				PORTC
#--------------------------------------------------------------------------------

peripheral18 (key=PORTC sfrs='TRISC LATC PORTC' type=port)
    iopin (key=RC0 dir=inout)
    iopin (key=RC1 dir=inout)
        cnpin (key=CCP2CN notify=CCP2)
    iopin (key=RC2 dir=inout)
        cnpin (key=CCP1CN notify=CCP1)
    iopin (key=RC3 dir=inout)
    iopin (key=RC4 dir=inout)
    iopin (key=RC5 dir=inout)
    iopin (key=RC6 dir=inout)
    iopin (key=RC7 dir=inout)

#--------------------------------------------------------------------------------
# 				CCP
#--------------------------------------------------------------------------------

peripheral18 (key=CCP1 sfrs='CCP1CON CCPR1L CCPR1H')
    pinfunc (key=CCP1 port=RC2 dir=inout)
    interrupt (name=CCP1INT enreg=PIE1 enmask=0x04 flgreg=PIR1 flgmask=0x04 prireg=IPR1 primask=0x04)
    specialevent (key=ADC)
#--
#  NOTE:  The address for the timers below is in fact not implemented because this part does not have a TMR3.
#  If we provided a 0x00 address, it would be considered invalid, so our intentions in using this address  
#  are solely to populate the database with the timers.
    timers (addr=0xFB1 mask=0x00)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
#--

#--------------------------------------------------------------------------------
# 				OSC
#--------------------------------------------------------------------------------

peripheral18 (key=PMOSC sfrs='OSCCON')
    pinfunc (key=OSC1 port=RA7 dir=out)
    pinfunc (key=OSC2 port=RA6 dir=out)
    pinfunc (key=T1OSCI port=RC1 dir=in)
        nextp (nextperiph=CCP2 nextpin=CCP2)
    pinfunc (key=T1OSCO port=RC0 dir=out)
        nextp (nextperiph=TMR1 nextpin=T1CKI)
        nextp (nextperiph=TMR3 nextpin=T3CKI)

#--------------------------------------------------------------------------------
# 				MCLR
#--------------------------------------------------------------------------------

peripheral18 (key=MCLR)
    pinfunc (key=MCLR port=RE3 dir=in)

#--------------------------------------------------------------------------------
# 				PSP
#--------------------------------------------------------------------------------

peripheral18 (key=PSP)
