
format=0.1

#device=PIC18F4431
# DOS: DOS-00373
# PS:  DS-30500
# DS:  DS-39616

vpp (range=9.000-13.250 dflt=13.000)
vdd (range=2.125-5.500 dfltrange=4.250-5.500 nominal=5.000)

pgming (memtech=ee tries=1 lvpthresh=4.500 panelsize=0x2000)
    wait (pgm=1000 lvpgm=1000 eedata=4000 cfg=5000 userid=5000 erase=10000 lverase=1000)
    latches(pgm=8 eedata=2 userid=8 cfg=2 rowerase=64)   	

pgmmem (region=0x0-0x3FFF)
eedata (region=0x00-0xff)
cfgmem (region=0x300000-0x30000D)
testmem (region=0x200000-0x2000BF)
userid (region=0x200000-0x200007)
devid (region=0x3FFFFE-0x3FFFFF idmask=0xFFE0 id=0x0880)
    ver (id=0x0880 desc="a0")
    ver (id=0x0881 desc="a1")

#
# The end address has been changed from a 0x2B to a 0x37 for the ICD2
bkbgvectmem (region=0x200028-0x200037)

NumBanks=16
AccessBankSplitOffset=0x60
UnusedBankMask=0x7FF8

UnusedRegs (0xf00-0xf5f)
UnusedRegs (0xf85-0xf86)
UnusedRegs (0xf8e-0xf8f)
UnusedRegs (0xf97-0xf98)
UnusedRegs (0xf9c-0xf9c)
UnusedRegs (0xfb1-0xfb5)
UnusedRegs (0xfc5-0xfc5)
UnusedRegs (0xfd4-0xfd4)



                               # ---------------#
#------------------------------# CORE Registers #------------------------------------------------#
                               # ---------------#

sfr (key=TOS addr=0xFFD size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - TOS' width='1 1 1 21')
sfr (key=TOSU addr=0xFFF size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - TOSU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TOSH addr=0xFFE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TOSL addr=0xFFD size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TOSL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=STKPTR addr=0xFFC size=1 access='rc rc u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='STKFUL STKUNF - STKPTR' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=PCLAT addr=0xFF9 size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - PCLAT' width='1 1 1 21')
sfr (key=PCLATU addr=0xFFB size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PCLATH addr=0xFFA size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PCL addr=0xFF9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=TBLPTR addr=0xFF6 size=3 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - ACSS TBLPTR' width='1 1 1 21')
sfr (key=TBLPTRU addr=0xFF8 size=1 access='u u rw rw rw rw rw rw')
    # NOTE: The ACSS bit allows access to the device configuration bits
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACSS TBLPTRU' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TBLPTRH addr=0xFF7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TBLPTRL addr=0xFF6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TBLPTRL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=TABLAT addr=0xFF5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TABLAT' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=PROD addr=0xFF3 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='PROD' width='16')
sfr (key=PRODH addr=0xFF4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODH' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PRODL addr=0xFF3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='PRODL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=INTCON addr=0xFF2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='0000000x' mclr='0000000u')
    bit (names='GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    # NOTE: When IPEN (bit 7) in the RCON register is 0 use the following bit names
    qbit (names='GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    # NOTE: When IPEN (bit 7) in the RCON register is 1 use the following bit names
    qbit (names='GIEH GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    bit (tag=scl names='GIE_GIEH PEIE_GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=INTCON2 addr=0xFF1 size=1 access='rw rw rw rw u rw u rw')
    reset (por='1111-1-1' mclr='1111-1-1')
    bit (names='nRBPU INTEDG0 INTEDG1 INTEDG2 - TMR0IP - RBIP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=INTCON3 addr=0xFF0 size=1 access='rw rw u rw rw u rw rw')
    reset (por='11-00-00' mclr='11-00-00')
    bit (names='INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=INDF0 addr=0xFEF size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF0' width='8')
sfr (key=POSTINC0 addr=0xFEE size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC0' width='8')
sfr (key=POSTDEC0 addr=0xFED size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC0' width='8')
sfr (key=PREINC0 addr=0xFEC size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC0' width='8')
sfr (key=PLUSW0 addr=0xFEB size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW0' width='8')

sfr (key=FSR0 addr=0xFE9 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR0' width='1 1 1 1 12')
sfr (key=FSR0H addr=0xFEA size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR0H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR0L addr=0xFE9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR0L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=WREG addr=0xFE8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='WREG' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=rw)
sfr (key=INDF1 addr=0xFE7 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF1' width='8')
sfr (key=POSTINC1 addr=0xFE6 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC1' width='8')
sfr (key=POSTDEC1 addr=0xFE5 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC1' width='8')
sfr (key=PREINC1 addr=0xFE4 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC1' width='8')
sfr (key=PLUSW1 addr=0xFE3 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW1' width='8')

sfr (key=FSR1 addr=0xFE1 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR1' width='1 1 1 1 12')
sfr (key=FSR1H addr=0xFE2 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----uuuu')
    bit (names='- - - - FSR1H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR1L addr=0xFE1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR1L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=BSR addr=0xFE0 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - BSR' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=INDF2 addr=0xFDF size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF2' width='8')
sfr (key=POSTINC2 addr=0xFDE size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTINC2' width='8')
sfr (key=POSTDEC2 addr=0xFDD size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='POSTDEC2' width='8')
sfr (key=PREINC2 addr=0xFDC size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PREINC2' width='8')
sfr (key=PLUSW2 addr=0xFDB size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='PLUSW2' width='8')

sfr (key=FSR2 addr=0xFD9 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='- - - - FSR2' width='1 1 1 1 12')
sfr (key=FSR2H addr=0xFDA size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - FSR2H' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=FSR2L addr=0xFD9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR2L' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=STATUS addr=0xFD8 size=1 access='u u u rw rw rw rw rw')
    reset (por='---xxxxx' mclr='---uuuuu')
    bit (names='- - - N OV Z DC C')
sfr (key=OSCCON addr=0xFD3 size=1 access='rw rw rw rw r r rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='IDLEN IRCF OSTS FLTS SCS' width='1 3 1 1 2')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=LVDCON addr=0xFD2 size=1 access='u u r rw rw rw rw rw')
    reset (por='--000101' mclr='--000101')
    bit (names='- - IRVST LVDEN LVDL' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=WDTCON addr=0xFD1 size=1 access='r r r r r r r rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WDT SWDTEN' width='7 1')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=RCON addr=0xFD0 size=1 access='rw u u rw rw rw rw rw')
    reset (por='0--111qq' mclr='0--qqquu')
    bit (names='IPEN - - nRI nTO nPD nPOR nBOR')
    stimulus (scl=r regfiles=w pcfiles=rw)

sfr (key=IPR3 addr=0xFA5 size=1 access='u u u rw rw rw rw rw')
    reset (por='---11111' mclr='---11111')
    bit (names='- - - PTIP IC3DRIP IC2QEIP IC1IP TMR5IP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR3 addr=0xFA4 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PTIF IC3DRIF IC2QEIF IC1IF TMR5IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIE3 addr=0xFA3 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PTIE IC3DRIE IC2QEIE IC1IE TMR5IE')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=IPR2 addr=0xFA2 size=1 access='rw u u rw u rw u rw')
    reset (por='1--1-1-1' mclr='1--1-1-1')
    bit (names='OSFIP - - EEIP - LVDIP - CCP2IP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR2 addr=0xFA1 size=1 access='rw u u rw u rw u rw')
    reset (por='0--0-0-0' mclr='0--0-0-0')
    bit (names='OSFIF - - EEIF - LVDIF - CCP2IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIE2 addr=0xFA0 size=1 access='rw u u rw u rw u rw')
    reset (por='0--0-0-0' mclr='0--0-0-0')
    bit (names='OSFIE - - EEIE - LVDIE - CCP2IE')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=IPR1 addr=0xF9F size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-1111111' mclr='-1111111')
    bit (names='- ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR1 addr=0xF9E size=1 access='u rw r r rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF')
    bit (tag=scl names='- ADIF - - SSPIF CCP1IF TMR2IF TMR1IF')
	stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIE1 addr=0xF9D size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # ---------------------#
#------------------------------# Oscillator Registers #----------------------------------------------------------------------------#
                               # ---------------------#

sfr (key=OSCTUNE addr=0xF9B size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - TUN' width='1 1 6')

                               # ----------------#
#------------------------------# PORTA Registers #-------------------------------------------------#
                               # ----------------#

# NOTE: Bits 6 and 7 of PORTA, LATA, and TRISA are configured as port pins based on ascillator modes.  
#       When used as oscillator pins, they read '0'.

sfr (key=PORTA addr=0xF80 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xx000000' mclr='uu000000')
    bit (names='RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATA addr=0xF89 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0')
    bit (tag=scl names='LATA' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISA addr=0xF92 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTB Registers #-----------------------------------------------------------------------------------------#
                               # ----------------#

sfr (key=PORTB addr=0xF81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0')
    bit (tag=scl names='RB' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=TRISB addr=0xF93 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0')
    bit (tag=scl names='TRISB' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=LATB addr=0xF8A size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0')
    bit (tag=scl names='LATB' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTC Registers #---------------------------------------#
                               # ----------------#

sfr (key=PORTC addr=0xF82 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATC addr=0xF8B size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0')
    bit (tag=scl names='LATC' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISC addr=0xF94 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTD Registers #-----------------------------------------------------------------------------------------#
                               # ----------------#

sfr (key=PORTD addr=0xF83 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0')
    bit (tag=scl names='RD' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATD addr=0xF8C size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0')
    bit (tag=scl names='LATD' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISD addr=0xF95 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0')
    bit (tag=scl names='TRISD' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ----------------#
#------------------------------# PORTE Registers #------------------------------------------------------#
                               # ----------------#

sfr (key=PORTE addr=0xF84 size=1 access='u u u u r rw rw rw')
    reset (por='----x000' mclr='----u000')
    bit (names='- - - - RE3 RE2 RE1 RE0')
    bit (tag=scl names='RE' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=LATE addr=0xF8D size=1 access='u u u u u rw rw rw')
    reset (por='-----xxx' mclr='-----uuu')
    bit (names='- - - - - LATE2 LATE1 LATE0')
    bit (tag=scl names='LATE' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISE addr=0xF96 size=1 access='u u u u u rw rw rw')
    reset (por='-----111' mclr='-----111')
    bit (names='- - - - - TRISE2 TRISE1 TRISE0')
    bit (tag=scl names='TRISE' width='8')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# ADC Registers #----------------------------------------------------------------------------#
                               # --------------#

sfr (key=ADRES addr=0xFC3 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='ADRES' width='16')
sfr (key=ADRESH addr=0xFC4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESH' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=ADRESL addr=0xFC3 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='ADRESL' width='8')
    stimulus (scl=rwb type=int regfiles=r)

sfr (key=ADCON0 addr=0xFC2 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - ACONV ACSCH ACMOD GO/nDONE ADON' width='1 1 1 1 2 1 1')
    bit (tag=scl names='- - ACONV ACSCH ACMOD GO_nDONE ADON' width='1 1 1 1 2 1 1')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON1 addr=0xFC1 size=1 access='rw rw u rw r r r r')
    reset (por='00-00000' mclr='00-00000')
    bit (names='VCFG - FIFOEN BFEMT BFOVFL ADPNT' width='2 1 1 1 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON2 addr=0xFC0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='ADFM ACQT ADCS' width='1 4 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=ADCON3 addr=0xF9A size=1 access='rw rw u rw rw rw rw rw')
    reset (por='00-00000' mclr='00-00000')
    bit (names='ADRS - SSRC' width='2 1 5')
    stimulus (scl=rwb regfiles=w)

sfr (key=ADCHS addr=0xF99 size=1 access='rw rw rw rw rw rw rw rw')
# Guessing at access masks because latest DOS does not provide an ADCHS register.
    reset (por='00000000' mclr='00000000')
    bit (names='SDSEL SBSEL SCSEL SASEL' width='2 2 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=ANSEL1 addr=0xFB9 size=1 access='u u u u u u u rw')
# Guessing at access masks because latest DOS does not provide an ANSEL1 register.
    reset (por='-------1' mclr='-------1')
    bit (names='- - - - - - - AN8')
    stimulus (scl=rwb regfiles=w)
sfr (key=ANSEL0 addr=0xFB8 size=1 access='rw rw rw rw rw rw rw rw')
# Guessing at access masks because latest DOS does not provide an ANSEL0 register.
    reset (por='11111111' mclr='11111111')
    bit (names='AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0')
    stimulus (scl=rwb regfiles=w)


                               # --------------#
#------------------------------# CCP Registers #----------------------------------------------------------------------------#
                               # --------------#

sfr (key=CCPR1 addr=0xFBE size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='CCPR1' width='16')
sfr (key=CCPR1H addr=0xFBF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1H' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=CCPR1L addr=0xFBE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR1L' width='8')
    stimulus (scl=rwb type=int regfiles=w)

sfr (key=CCP1CON addr=0xFBD size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC1B CCP1M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)

sfr (key=CCPR2 addr=0xFBB size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='CCPR2' width='16')
sfr (key=CCPR2H addr=0xFBC size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2H' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=CCPR2L addr=0xFBB size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CCPR2L' width='8')
    stimulus (scl=rwb type=int regfiles=w)

sfr (key=CCP2CON addr=0xFBA size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - DC2B CCP2M' width='1 1 2 4')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# SSP Registers #----------------------------------------------------------------------------#
                               # --------------#

sfr (key=SSPBUF addr=0xFC9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='SSPBUF' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=SSPADD addr=0xFC8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SSPADD' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
# All bits are rw so they can be simulated
# sfr (key=SSPSTAT addr=0xFC7 size=1 access='rw rw r r r r r r')
sfr (key=SSPSTAT addr=0xFC7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SMP CKE D/nA P S R/nW UA BF')
#    bit (tag=scl names='SMP CKE D_nA P S R_nW UA BF')
sfr (key=SSPCON addr=0xFC6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='WCOL SSPOV SSPEN CKP SSPM' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # -----------------#
#------------------------------# TIMER0 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=TMR0 addr=0xFD6 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='TMR0' width='16')
sfr (key=TMR0H addr=0xFD7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR0H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR0L addr=0xFD6 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)

sfr (key=T0CON addr=0xFD5 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='TMR0ON T08BIT T0CS T0SE PSA T0PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER1 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=TMR1 addr=0xFCE size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='TMR1' width='16')
sfr (key=TMR1H addr=0xFCF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR1L addr=0xFCE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)

sfr (key=T1CON addr=0xFCD size=1 access='rw rw rw rw r r rw rw')
    reset (por='00000000' mclr='u0uuuuuu')
    bit (names='RD16 T1RUN T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER2 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=TMR2 addr=0xFCC size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='TMR2' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=PR2 addr=0xFCB size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR2' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=T2CON addr=0xFCA size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- TOUTPS TMR2ON T2CKPS' width='1 4 1 2')
    stimulus (scl=rwb regfiles=w)

                               # -----------------#
#------------------------------# TIMER5 Registers #-------------------------------------------------#
                               # -----------------#

sfr (key=T5CON addr=0xFB7 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='T5SEN nRESEN T5MOD T5PS nT5SYNC TMR5CS TMR5ON' width='1 1 1 2 1 1 1')
    stimulus (scl=rwb regfiles=w)

sfr (key=PR5 addr=0xF90 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='PR5' width='16')
sfr (key=PR5H addr=0xF91 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR5H' width='8')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=PR5L addr=0xF90 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PR5L' width='8')
    stimulus (scl=rwb type=int regfiles=w)

sfr (key=TMR5 addr=0xF87 size=2 flags=j)
    # NOTE: The j flag means all these registers together form one larger register
    bit (names='TMR5' width='16')
sfr (key=TMR5H addr=0xF88 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR5H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR5L addr=0xF87 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR5L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)

                               # -----------------#
#------------------------------# EEPROM Registers #----------------------------------------------------------------------------#
                               # -----------------#

sfr (key=EEADR addr=0xFA9 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=EEDATA addr=0xFA8 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='EEDATA' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=EECON2 addr=0xFA7 size=1 flags=w access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')
sfr (key=EECON1 addr=0xFA6 size=1 access='rw rw u rw rw rw rs rs')
    reset (por='xx-0x000' mclr='uu-0u000')
    bit (names='EEPGD CFGS - FREE WRERR WREN WR RD')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # ------------------------#
#------------------------------# Enhanced UART Registers #-------------------------------------------------#
                               # ------------------------#

sfr (key=SPBRGH addr=0xFB0 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRGH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=SPBRG addr=0xFAF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SPBRG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCREG addr=0xFAE size=1 access='r r r r r r r r')
    reset (por='00000000' mclr='00000000')
    bit (names='RCREG' width='8')
    stimulus (scl=rb regfiles=rp)
sfr (key=TXREG addr=0xFAD size=1 access='w w w w w w w w')
    reset (por='00000000' mclr='00000000')
    bit (names='TXREG' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=TXSTA addr=0xFAC size=1 access='rw rw rw rw u rw r rw')
    reset (por='0000-010' mclr='0000-010')
    bit (names='CSRC TX9 TXEN SYNC - BRGH TRMT TX9D')
    stimulus (scl=rwb regfiles=w)
sfr (key=RCSTA addr=0xFAB size=1 access='rw rw rw rw rw r r r')
    reset (por='0000000x' mclr='0000000x')
    bit (names='SPEN RX9 SREN CREN ADDEN FERR OERR RX9D')
    stimulus (scl=rwb regfiles=w)
sfr (key=BAUDCTL addr=0xFAA size=1 access='u r u rw rw u rw rw')
# Reset values are inconsistent in data sheet. These values may be wrong.
    reset (por='-1-10-00' mclr='-1-10-00')
    bit (names='- RCIDL - SCKP BRG16 - WUE ABDEN')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# PWM Registers #-------------------------------------------------#
                               # --------------#

# Guessing at the read write masks for the remaining sfrs because no registers were provided in the DOS

sfr (key=PTCON0 addr=0xF7F size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='PTOPS PTCKPS PTMOD' width='4 2 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTCON1 addr=0xF7E size=1 access='rw r u u u u u u')
    reset (por='00------' mclr='00------')
    bit (names='PTEN PTDIR - - - - - -')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTMRL addr=0xF7D size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PTMRL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTMRH addr=0xF7C size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - PTMRH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTPERL addr=0xF7B size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='PTPERL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PTPERH addr=0xF7A size=1 access='u u u u rw rw rw rw')
    reset (por='----1111' mclr='----1111')
    bit (names='- - - - PTPERH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC0L addr=0xF79 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC0L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC0H addr=0xF78 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC0H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC1L addr=0xF77 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC1L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC1H addr=0xF76 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC1H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC2L addr=0xF75 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC2L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC2H addr=0xF74 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC2H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC3L addr=0xF73 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PDC3L' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PDC3H addr=0xF72 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - PDC3H' width='1 1 6')
    stimulus (scl=rwb regfiles=w)

sfr (key=SEVTCMPL addr=0xF71 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='SEVTCMPL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=SEVTCMPH addr=0xF70 size=1 access='u u u u rw rw rw rw')
    reset (por='----0000' mclr='----0000')
    bit (names='- - - - SEVTCMPH' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)

sfr (key=PWMCON0 addr=0xF6F size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-1010000' mclr='-1010000')
    bit (names='- PWMEN PMOD' width='1 3 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=PWMCON1 addr=0xF6E size=1 access='rw rw rw rw rw u rw rw')
    reset (por='00000-00' mclr='00000-00')
    bit (names='SEVOPS SEVTDIR - UDIS OSYNC' width='4 1 1 1 1')
    stimulus (scl=rwb regfiles=w)

sfr (key=DTCON addr=0xF6D size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='DTAPS DTA' width='2 6')
    stimulus (scl=rwb regfiles=w)
sfr (key=FLTCONFIG addr=0xF6C size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- FLTBS FLTBMOD FLTBEN FLTCON FLTAS FLTAMOD FLTAEN')
    stimulus (scl=rwb regfiles=w)
sfr (key=OVDCOND addr=0xF6B size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='POVD' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=OVDCONS addr=0xF6A size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='POUT' width='8')
    stimulus (scl=rwb regfiles=w)

                               # ------------------------#
#------------------------------# Input Capture Registers #-------------------------------------------------#
                               # ------------------------#

sfr (key=CAP1CON addr=0xF63 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP1REN CAP1TMR - CAP1M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP2CON addr=0xF62 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP2REN CAP2TMR - CAP2M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=CAP3CON addr=0xF61 size=1 access='u rw rw u rw rw rw rw')
    reset (por='-10-0000' mclr='-10-0000')
    bit (names='- CAP3REN CAP3TMR - CAP3M' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)

                               # --------------#
#------------------------------# QEI Registers #-------------------------------------------------#
                               # --------------#

sfr (key=QEICON addr=0xFB6 size=1 access='rw u rw rw rw rw rw rw')
# Guessing at access masks because latest DOS does not provide a QEICON register.
    reset (por='0-000000' mclr='0-000000')
    bit (names='nVELM - UP/nDOWN QEIM PDEC' width='1 1 1 3 2')
    bit (tag=scl names='nVELM - UP_nDOWN QEIM PDEC' width='1 1 1 3 2')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

                               # -----------------------#
#------------------------------# Noise Filter Registers #-------------------------------------------------#
                               # -----------------------#

# This register is assocated with TMR5

sfr (key=DFLTCON addr=0xF60 size=1 access='u rw rw rw rw rw rw rw')
    reset (por='-0000000' mclr='-0000000')
    bit (names='- FLT4EN FLT3EN FLT2EN FLT1EN FLTCK' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP1BUFH addr=0xF69 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP1BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=VELRH addr=0xF69 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='VELRH' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
# ---------------------------------------------------------------------------


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP1BUFL addr=0xF68 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP1BUFL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=VELRL addr=0xF68 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='VELRL' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
# ---------------------------------------------------------------------------


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP2BUFH addr=0xF67 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP2BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=POSCNTH addr=0xF67 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='POSCNTH' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
# ---------------------------------------------------------------------------


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP2BUFL addr=0xF66 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP2BUFL' width='8')
    stimulus (scl=rwb)
sfr (key=POSCNTL addr=0xF66 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='POSCNTL' width='8')
    stimulus (scl=rwb)
# ---------------------------------------------------------------------------


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP3BUFH addr=0xF65 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP3BUFH' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=MAXCNTH addr=0xF65 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='MAXCNTH' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
# ---------------------------------------------------------------------------


# ---------------------------------------------------------------------------
# Alternate SFRs: The following registers are mapped to the same address.
#
sfr (key=CAP3BUFL addr=0xF64 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='CAP3BUFL' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=MAXCNTL addr=0xF64 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='MAXCNTL' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
# ---------------------------------------------------------------------------

                               # -------------------#
#------------------------------# Configuration Bits #------------------------------------#
                               # -------------------#

cfgbits (key=CONFIG1H addr=0x300001 unused=0x0)
    field (key=OSC mask=0xF desc="Oscillator")
        setting (req=0xC value=0xC desc="11XX EXT RC-CLKOUT on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xE value=0xA desc="101X EXT RC-CLKOUT on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xF value=0x9 desc="INT RC-CLKOUT on RA6,Port on RA7")
        setting (req=0xF value=0x8 desc="INT RC-Port on RA6,Port on RA7")
        setting (req=0xF value=0x7 desc="EXT RC-Port on RA6" freqmin=32000 freqmax=4000000)
        setting (req=0xF value=0x6 desc="HS-PLL enabled freq=4xFosc1" freqmin=16000000 freqmax=40000000)
        setting (req=0xF value=0x5 desc="EC-Port on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xF value=0x4 desc="EC-CLKOUT on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xF value=0x3 desc="0011 EXT RC-CLKOUT on RA6" freqmin=32000 freqmax=40000000)
        setting (req=0xF value=0x2 desc="HS" freqmin=4000000 freqmax=20000000)
        setting (req=0xF value=0x1 desc="XT" freqmin=1000000 freqmax=4000000)
        setting (req=0xF value=0x0 desc="LP" freqmin=32000 freqmax=200000)
    field (key=FCMEN mask=0x40 desc="Fail-Safe Clock Monitor Enable")
        setting (req=0x40 value=0x40 desc="Enabled")
        setting (req=0x40 value=0x0 desc="Disabled")
    field (key=IESO mask=0x80 desc="Internal External Switch Over Mode")
        setting (req=0x80 value=0x80 desc="Enabled")
	 setting (req=0x80 value=0x0 desc="Disabled")
cfgbits (key=CONFIG2L addr=0x300002 unused=0x0)
    field (key=PUT mask=0x1 desc="Power Up Timer")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x0 desc="Enabled")
    field (key=BODEN mask=0x2 desc="Brown Out Detect")
        setting (req=0x2 value=0x2 desc="Enabled")
        conflict (addr=0x300002 mask=0xC value=0xC cfmsg=3)
        setting (req=0x2 value=0x0 desc="Disabled")
    field (key=BODENV mask=0xC desc="Brown Out Voltage")
        setting (req=0xC value=0xC desc="Undefined")
        setting (req=0xC value=0x8 desc="2.7V")
        setting (req=0xC value=0x4 desc="4.2V")
        setting (req=0xC value=0x0 desc="4.5V")
cfgbits (key=CONFIG2H addr=0x300003 unused=0x0)
    field (key=WDT mask=0x1 desc="Watchdog Timer")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
    field (key=WDTPS mask=0x1E desc="Watchdog Postscaler")
        setting (req=0x1E value=0x1E desc="1:32768")
        setting (req=0x1E value=0x1C desc="1:16384")
        setting (req=0x1E value=0x1A desc="1:8192")
        setting (req=0x1E value=0x18 desc="1:4096")
        setting (req=0x1E value=0x16 desc="1:2048")
        setting (req=0x1E value=0x14 desc="1:1024")
        setting (req=0x1E value=0x12 desc="1:512")
        setting (req=0x1E value=0x10 desc="1:256")
        setting (req=0x1E value=0xE desc="1:128")
        setting (req=0x1E value=0xC desc="1:64")
        setting (req=0x1E value=0xA desc="1:32")
        setting (req=0x1E value=0x8 desc="1:16")
        setting (req=0x1E value=0x6 desc="1:8")
        setting (req=0x1E value=0x4 desc="1:4")
        setting (req=0x1E value=0x2 desc="1:2")
        setting (req=0x1E value=0x0 desc="1:1")
    field (key=WINEN mask=0x20 desc="Watchdog Timer Window")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
cfgbits (key=CONFIG3L addr=0x300004 unused=0x0)
    field (key=PWMPIN mask=0x4 desc="PWM Output Pin Reset")
        setting (req=0x4 value=0x4 desc="PWM outputs disabled upon RESET")
        setting (req=0x4 value=0x0 desc="PWM outputs drive active states upon RESET")
    field (key=LPOL mask=0x8 desc="Low-Side Transistors Polarity")
        setting (req=0x8 value=0x8 desc="PWM 0, 2, 4 and 6 are active high")
        setting (req=0x8 value=0x0 desc="PWM 0, 2, 4 and 6 are active low")
    field (key=HPOL mask=0x10 desc="High-Side Transistors Polarity")
        setting (req=0x10 value=0x10 desc="PWM 1, 3, 5, and 7 are active high")
        setting (req=0x10 value=0x0 desc="PWM 1, 3, 5, and 7 are active low")
    field (key=T1OSCMX mask=0x20 desc="Timer1 OSC")
        setting (req=0x20 value=0x20 desc="Low Power")
        setting (req=0x20 value=0x0 desc="Legacy")
cfgbits (key=CONFIG3H addr=0x300005 unused=0x0)
    field (key=FLTAMX mask=0x1 desc="FLTA Mux")
        setting (req=0x1 value=0x1 desc="FLTA input muxed with RC1")
        setting (req=0x1 value=0x0 desc="FLTA input muxed with RD4")
    field (key=SSPMX mask=0x4 desc="SSP I/O Mux")
        setting (req=0x4 value=0x4 desc="SCK/SCL, SDA/SDI and SDO are mux w/ RC5, RC4 and RC7 respectively.")
        setting (req=0x4 value=0x0 desc="SCK/SCL, SDA/SDI and SDO are mux w/ RD3, RD2 and RD1 respectively.")
    field (key=PWM4MX mask=0x8 desc="PWM4 Mux")
        setting (req=0x8 value=0x8 desc="PWM4 output muxed w/ RB5")
        setting (req=0x8 value=0x0 desc="PWM4 output muxed w/ RD5")
    field (key=EXCLKMX mask=0x10 desc="TMR0/T5CKI EXT CLK Mux")
# NOTE:  This EXCLKMX bit is needed only on A0 silicon.  For A1 silicon, this bit will be reserved.
        setting (req=0x10 value=0x10 desc="TMR0/T5CKI external clock input is multiplexed with RC3")
        setting (req=0x10 value=0x0 desc="TMR0/T5CKI external clock input is multiplexed with RD0")
    field (key=MCLRE mask=0x80 desc="Master Clear Enable")
        setting (req=0x80 value=0x80 desc="MCLR enabled, RE3 input disabled")
        setting (req=0x80 value=0x0 desc="RE3 input enabled, MCLR disabled")
cfgbits (key=CONFIG4L addr=0x300006 unused=0x0)
    field (key=BACKBUG mask=0x80 desc="Background Debug" flags=h)
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
    field (key=LVP mask=0x4 desc="Low Voltage Program")
        setting (req=0x4 value=0x4 desc="Enabled")
        setting (req=0x4 value=0x0 desc="Disabled")
    field (key=STVR mask=0x1 desc="Stack Overflow Reset")
        setting (req=0x1 value=0x1 desc="Enabled")
        setting (req=0x1 value=0x0 desc="Disabled")
cfgbits (key=CONFIG5L addr=0x300008 unused=0x0)
    field (key=CP_0 mask=0x1 desc="Code Protect 00200-00FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x1 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x200-0xFFF)
    field (key=CP_1 mask=0x2 desc="Code Protect 01000-01FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x2 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x1000-0x1FFF)
    field (key=CP_2 mask=0x4 desc="Code Protect 02000-02FFF")
        setting (req=0x4 value=0x4 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x4 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x2000-0x2FFF)
    field (key=CP_3 mask=0x8 desc="Code Protect 03000-03FFF")
        setting (req=0x8 value=0x8 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x8 value=0x00 desc="Enabled")
            checksum (type=0x27 protregion=0x3000-0x3FFF)
cfgbits (key=CONFIG5H addr=0x300009 unused=0x0)
    field (key=CPD mask=0x80 desc="Data EE Read Protect")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
    field (key=CPB mask=0x40 desc="Code Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x40 value=0x0 desc="Enabled")
            checksum (type=0x27 protregion=0x0-0x1FF)
cfgbits (key=CONFIG6L addr=0x30000A unused=0x0)
    field (key=WRT_0 mask=0x1 desc="Table Write Protect 00200-00FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x00 desc="Enabled")
    field (key=WRT_1 mask=0x2 desc="Table Write Protect 01000-01FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x00 desc="Enabled")
    field (key=WRT_2 mask=0x4 desc="Table Write Protect 02000-02FFF")
        setting (req=0x4 value=0x4 desc="Disabled")
        setting (req=0x4 value=0x00 desc="Enabled")
    field (key=WRT_3 mask=0x8 desc="Table Write Protect 03000-03FFF")
        setting (req=0x8 value=0x8 desc="Disabled")
        setting (req=0x8 value=0x00 desc="Enabled")
cfgbits (key=CONFIG6H addr=0x30000B unused=0x0)
    field (key=WRTD mask=0x80 desc="Data EE Write Protect")
        setting (req=0x80 value=0x80 desc="Disabled")
        setting (req=0x80 value=0x0 desc="Enabled")
    field (key=WRTB mask=0x40 desc="Table Write Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")
    field (key=WRTC mask=0x20 desc="Config. Write Protect")
        setting (req=0x20 value=0x20 desc="Disabled")
        setting (req=0x20 value=0x0 desc="Enabled")
cfgbits (key=CONFIG7L addr=0x30000C unused=0x0)
    field (key=EBTR_0 mask=0x1 desc="Table Read Protect 00200-00FFF")
        setting (req=0x1 value=0x1 desc="Disabled")
        setting (req=0x1 value=0x00 desc="Enabled")
    field (key=EBTR_1 mask=0x2 desc="Table Read Protect 01000-01FFF")
        setting (req=0x2 value=0x2 desc="Disabled")
        setting (req=0x2 value=0x00 desc="Enabled")
    field (key=EBTR_2 mask=0x4 desc="Table Read Protect 02000-02FFF")
        setting (req=0x4 value=0x4 desc="Disabled")
        setting (req=0x4 value=0x00 desc="Enabled")
    field (key=EBTR_3 mask=0x8 desc="Table Read Protect 03000-03FFF")
        setting (req=0x8 value=0x8 desc="Disabled")
        setting (req=0x8 value=0x00 desc="Enabled")
cfgbits (key=CONFIG7H addr=0x30000D unused=0x0)
    field (key=EBTRB mask=0x40 desc="Table Read Protect Boot")
        setting (req=0x40 value=0x40 desc="Disabled")
        setting (req=0x40 value=0x0 desc="Enabled")


                               # ------------#
#------------------------------# Peripherals #------------------------------------#
                               # ------------#

#--------------------------------------------------------------------------------
# 				TIMERs
#--------------------------------------------------------------------------------

peripheral18 (key=TMR0 sfrs='TMR0H TMR0L T0CON')
    pinfunc (key=T0CKI port=multi dir=in)
        portpins (muxaddr=0x300005 muxmask=0x10)
            setting (muxval=0x00 port=RD0 dir=in)
            setting (muxval=0x10 port=RC3 dir=in)
    interrupt (name=TMR0INT enreg=INTCON enmask=0x20 flgreg=INTCON flgmask=0x04 prireg=INTCON2 primask=0x04)

peripheral18 (key=TMR1 sfrs='TMR1H TMR1L T1CON')
    pinfunc (key=T1CKI port=RC0 dir=in)
    interrupt (name=TMR1INT enreg=PIE1 enmask=0x01 flgreg=PIR1 flgmask=0x01 prireg=IPR1 primask=0x01)

peripheral18 (key=TMR2 sfrs='TMR2 PR2 T2CON')
    interrupt (name=TMR2INT enreg=PIE1 enmask=0x02 flgreg=PIR1 flgmask=0x02 prireg=IPR1 primask=0x02)

peripheral18 (key=TMR5 sfrs='T5CON PR5H PR5L TMR5H TMR5L')
    pinfunc (key=T5CKI port=multi dir=in)
        portpins (muxaddr=0x300005 muxmask=0x10)
            setting (muxval=0x00 port=RD0 dir=in)
            setting (muxval=0x10 port=RC3 dir=in)
    interrupt (name=TMR5INT enreg=PIE3 enmask=0x01 flgreg=PIR3 flgmask=0x01 prireg=IPR3 primask=0x01)

#--------------------------------------------------------------------------------
# 				ADC
#--------------------------------------------------------------------------------

peripheral18 (key=ADC sfrs='ADCON0 ADCON1 ADCON2 ADCON3 ADRESL ADRESH ADCHS ANSEL0 ANSEL1')
    pinfunc (key=AN0 port=RA0 dir=in)
    pinfunc (key=AN1 port=RA1 dir=in)
    pinfunc (key=AN2 port=RA2 dir=in)
    pinfunc (key=AN3 port=RA3 dir=in)
    pinfunc (key=AN4 port=RA4 dir=in)
    pinfunc (key=AN5 port=RA5 dir=in)
    pinfunc (key=AN6 port=RE0 dir=in)
    pinfunc (key=AN7 port=RE1 dir=in)
    pinfunc (key=AN8 port=RE2 dir=in)
    access (key=ADCON1 mode=AD_FIFO_BUFF)
    access (key=ADCON2 mode=AD_ACQUISITION)
    interrupt (name=ADC enreg=PIE1 enmask=0x40 flgreg=PIR1 flgmask=0x40 prireg=IPR1 primask=0x40)

#--------------------------------------------------------------------------------
# 				UARTs
#--------------------------------------------------------------------------------

peripheral18 (key=UART1 sfrs='SPBRGH SPBRG RCREG TXREG TXSTA RCSTA BAUDCTL')
    pinfunc (key=U1RX port=RC7 dir=in)
        nextp (nextperiph=SSP nextpin=SDO)
    pinfunc (key=U1TX port=RC6 dir=out)
        nextp (nextperiph=SSP nextpin=SS)
    interrupt (name=RXINT1 enreg=PIE1 enmask=0x20 flgreg=PIR1 flgmask=0x20 prireg=IPR1 primask=0x20)
    interrupt (name=TXINT1 enreg=PIE1 enmask=0x10 flgreg=PIR1 flgmask=0x10 prireg=IPR1 primask=0x10)

#--------------------------------------------------------------------------------
# 				PORTA
#--------------------------------------------------------------------------------

peripheral18 (key=PORTA sfrs='TRISA LATA PORTA' type=port)
    iopin (key=RA0 dir=inout)
    iopin (key=RA1 dir=inout)
    iopin (key=RA2 dir=inout)
        cnpin (key=IC1CN notify=IC1)
    iopin (key=RA3 dir=inout)
        cnpin (key=IC2CN notify=IC2)
    iopin (key=RA4 dir=inout)
        cnpin (key=IC3CN notify=IC3)
    iopin (key=RA5 dir=inout)
    iopin (key=RA6 dir=inout)
    iopin (key=RA7 dir=inout)

#--------------------------------------------------------------------------------
# 				PORTB
#--------------------------------------------------------------------------------

peripheral18 (key=PORTB sfrs='TRISB LATB PORTB' type=port)
    iopin (key=RB0 dir=inout)
    iopin (key=RB1 dir=inout)
    iopin (key=RB2 dir=inout)
    iopin (key=RB3 dir=inout)
    iopin (key=RB4 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI0)
    iopin (key=RB5 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI1)
    iopin (key=RB6 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI2)
    iopin (key=RB7 dir=inout)
        cnint (key=KBIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=INTCON2 primask=0x01 cnkey=KBI3)

#--------------------------------------------------------------------------------
# 				PORTC
#--------------------------------------------------------------------------------

peripheral18 (key=PORTC sfrs='TRISC LATC PORTC' type=port)
    iopin (key=RC0 dir=inout)
    iopin (key=RC1 dir=inout)
        cnpin (key=CCP2CN notify=CCP2)
        cnpin (key=PWMFLTA notify=PWM)
    iopin (key=RC2 dir=inout)
        cnpin (key=CCP1CN notify=CCP1)
        cnpin (key=PWMFLTB notify=PWM)
    iopin (key=RC3 dir=inout)
        extint (key=INT0 enreg=INTCON enmask=0x10 flgreg=INTCON flgmask=0x02 prireg=NONE primask=0x00)
    iopin (key=RC4 dir=inout)
        extint (key=INT1 enreg=INTCON3 enmask=0x08 flgreg=INTCON3 flgmask=0x01 prireg=INTCON3 primask=0x40)
    iopin (key=RC5 dir=inout)
        extint (key=INT2 enreg=INTCON3 enmask=0x10 flgreg=INTCON3 flgmask=0x02 prireg=INTCON3 primask=0x80)
    iopin (key=RC6 dir=inout)
    iopin (key=RC7 dir=inout)

#--------------------------------------------------------------------------------
# 				PORTD
#--------------------------------------------------------------------------------

peripheral18 (key=PORTD sfrs='TRISD LATD PORTD' type=port)
    iopin (key=RD0 dir=inout)
    iopin (key=RD1 dir=inout)
    iopin (key=RD2 dir=inout)
    iopin (key=RD3 dir=inout)
    iopin (key=RD4 dir=inout)
        cnpin (key=PWMFLTA notify=PWM)
    iopin (key=RD5 dir=inout)
    iopin (key=RD6 dir=inout)
    iopin (key=RD7 dir=inout)

#--------------------------------------------------------------------------------
# 				PORTE
#--------------------------------------------------------------------------------

peripheral18 (key=PORTE sfrs='TRISE LATE PORTE' type=port)
    iopin (key=RE0 dir=inout)
    iopin (key=RE1 dir=inout)
    iopin (key=RE2 dir=inout)
    iopin (key=RE3 dir=in)

#--------------------------------------------------------------------------------
# 				CCP
#--------------------------------------------------------------------------------

peripheral18 (key=CCP1 sfrs='CCP1CON CCPR1L CCPR1H')
    pinfunc (key=CCP1 port=RC2 dir=inout)
    interrupt (name=CCP1INT enreg=PIE1 enmask=0x04 flgreg=PIR1 flgmask=0x04 prireg=IPR1 primask=0x04)
#--
#  NOTE:  The address for the timers below is in fact not implemented because this part does not have a TMR3.
#  If we provided a 0x00 address, it would be considered invalid, so our intentions in using this address  
#  are solely to populate the database with the timers.
    timers (addr=0xFB1 mask=0x00)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
#--

peripheral18 (key=CCP2 sfrs='CCP2CON CCPR2L CCPR2H')
    pinfunc (key=CCP2 port=RC1 dir=inout)
    interrupt (name=CCP2INT enreg=PIE2 enmask=0x01 flgreg=PIR2 flgmask=0x01 prireg=IPR2 primask=0x01)
    specialevent (key=ADC)
#--
#  NOTE:  The address for the timers below is in fact not implemented because this part does not have a TMR3.
#  If we provided a 0x00 address, it would be considered invalid, so our intentions in using this address  
#  are solely to populate the database with the timers.
    timers (addr=0xFB1 mask=0x00)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
        setting (val=0x00 cc=TMR1 pwm=TMR2)
#--

#--------------------------------------------------------------------------------
# 				OSC
#--------------------------------------------------------------------------------

peripheral18 (key=PMOSC sfrs='OSCCON')
    pinfunc (key=OSC1 port=RA7 dir=out)
    pinfunc (key=OSC2 port=RA6 dir=out)
    pinfunc (key=T1OSCI port=RC1 dir=in)
        nextp (nextperiph=CCP2 nextpin=CCP2)
    pinfunc (key=T1OSCO port=RC0 dir=out)
        nextp (nextperiph=TMR1 nextpin=T1CKI)

#--------------------------------------------------------------------------------
# 				PWM
#--------------------------------------------------------------------------------

peripheral18 (key=PWM sfrs='PTCON0 PTCON1 PWMCON0 PWMCON1 DTCON OVDCOND OVDCONS FLTCONFIG PTMRH PTMRL PTPERH PTPERL SEVTCMPH SEVTCMPL PDC0H PDC0L PDC1H PDC1L PDC2H PDC2L PDC3H PDC3L')
    pinfunc (key=PWM0 port=RB0 dir=out)
    pinfunc (key=PWM1 port=RB1 dir=out)
    pinfunc (key=PWM2 port=RB2 dir=out)
    pinfunc (key=PWM3 port=RB3 dir=out)
    pinfunc (key=PWM4 port=multi dir=out)
        portpins (muxaddr=0x300005 muxmask=0x08)
            setting (muxval=0x00 port=RD5 dir=out)
            setting (muxval=0x08 port=RB5 dir=out)
    pinfunc (key=PWM5 port=RB4 dir=out)
    pinfunc (key=PWM6 port=RD6 dir=out)
    pinfunc (key=PWM7 port=RD7 dir=out)
    pinfunc (key=PWMFLTA port=multi dir=in)
        portpins (muxaddr=0x300005 muxmask=0x01)
            setting (muxval=0x00 port=RD4 dir=in)
            setting (muxval=0x01 port=RC1 dir=in)
    pinfunc (key=PWMFLTB port=RC2 dir=in)
    specialevent (key=ADC)
    interrupt (name=PWMINT enreg=PIE3 enmask=0x10 flgreg=PIR3 flgmask=0x10 prireg=IPR3 primask=0x10)

#--------------------------------------------------------------------------------
# 				Input Capture
#--------------------------------------------------------------------------------

peripheral18 (key=IC1 sfrs='CAP1CON CAP1BUFL')
    pinfunc (key=CAP1 port=RA2 dir=in)
#We use a false address below just to get the data because an address of 0x0 is considered invalid
    timers (addr=0xF mask=0x0)
        setting (val=0x00 key=TMR5)
    interrupt (name=IC1INT enreg=PIE3 enmask=0x02 flgreg=PIR3 flgmask=0x02 prireg=IPR3 primask=0x02)

peripheral18 (key=IC2 sfrs='CAP2CON CAP2BUFL')
    pinfunc (key=CAP2 port=RA3 dir=in)
#We use a false address below just to get the data because an address of 0x0 is considered invalid
    timers (addr=0xF mask=0x0)
        setting (val=0x00 key=TMR5)
    interrupt (name=IC2INT enreg=PIE3 enmask=0x04 flgreg=PIR3 flgmask=0x04 prireg=IPR3 primask=0x04)

peripheral18 (key=IC3 sfrs='CAP3CON CAP3BUFL')
    pinfunc (key=CAP3 port=RA4 dir=in)
#We use a false address below just to get the data because an address of 0x0 is considered invalid
    timers (addr=0xF mask=0x0)
        setting (val=0x00 key=TMR5)
    interrupt (name=IC3INT enreg=PIE3 enmask=0x08 flgreg=PIR3 flgmask=0x08 prireg=IPR3 primask=0x08)

#--------------------------------------------------------------------------------
# 				MCLR
#--------------------------------------------------------------------------------

peripheral18 (key=MCLR)
    pinfunc (key=MCLR port=RE3 dir=in)

#--------------------------------------------------------------------------------
# 				QEI
#--------------------------------------------------------------------------------

peripheral18 (key=QEI)

#--------------------------------------------------------------------------------
# 				SSP
#--------------------------------------------------------------------------------

peripheral18 (key=SSP)
