 
format=0.1

#device=PIC16F636
# DOS: DOS-00483
# PS:  DS-41204
# DS:  DS-41232

vpp (range=10.000-12.000  dflt=11.000)
vdd (range=2.000-5.500  dfltrange=4.500-5.500  nominal=5.000)

# Updated LVP Threshold
pgming (memtech=ee tries=1 lvpthresh=4.500)
    wait (pgm=2500 lvpgm=2500 eedata=6000 cfg=6000 userid=6000 erase=6000 lverase=2500)
    latches(pgm=4 eedata=1 userid=1 cfg=1 rowerase=16)   

pgmmem (region=0x00-0x7FF)
cfgmem (region=0x2007-0x2007)
# calmem (region=0x3FF-0x3FF) cal mem is at 2008, but does not need to be touched by the user
userid (region=0x2000-0x2003)
devid (region=0x2006-0x2006 idmask=0x3FE0 id=0x10A0)
eedata (region=0x0-0xff)
testmem (region=0x2000-0x203F)
bkbgvectmem (region=0x2004-0x2004)

# NOTE: The data sheet shows this as a 4 bank device. 
# Bank 2 mirrors bank 0 and bank 3 mirrors bank 1. 
NumBanks=4

MirrorRegs (0x0-0x0 0x80-0x80 0x100-0x100 0x180-0x180)
MirrorRegs (0x1-0x1 0x101-0x101)
MirrorRegs (0x2-0x4 0x82-0x84 0x102-0x104 0x182-0x184)
MirrorRegs (0x05-0x05 0x105-0x105)
MirrorRegs (0x7-0x7 0x107-0x107)
MirrorRegs (0xA-0xA 0x10A-0x10A)
MirrorRegs (0xB-0xB 0x8B-0x8B 0x10B-0x10B 0x18B-0x18B)
MirrorRegs (0x8A-0x8A 0x18A-0x18A)
MirrorRegs (0x70-0x7F 0xF0-0xFF 0x170-0x17F 0x1F0-0x1FF)
MirrorRegs (0x81-0x81 0x181-0x181)
MirrorRegs (0x85-0x85 0x185-0x185)
MirrorRegs (0x87-0x87 0x187-0x187)

UnusedRegs (0x06-0x06)
UnusedRegs (0x08-0x09)
UnusedRegs (0x0d-0x0d)
UnusedRegs (0x11-0x17)
UnusedRegs (0x1b-0x1f)
UnusedRegs (0x86-0x86)
UnusedRegs (0x88-0x89)
UnusedRegs (0x8d-0x8d)
UnusedRegs (0x91-0x93)
UnusedRegs (0x98-0x98)
UnusedRegs (0x9e-0x9f)
UnusedRegs (0xc0-0xef)
UnusedRegs (0x106-0x106)
UnusedRegs (0x108-0x109)
UnusedRegs (0x10c-0x10f)
UnusedRegs (0x115-0x16f)
UnusedRegs (0x186-0x186)
UnusedRegs (0x188-0x189)
UnusedRegs (0x18c-0x1ef)


sfr (key=INDF addr=0x0 size=1 flags=i access='u u u u u u u u')
    reset (por='--------' mclr='--------')
    bit (names='INDF' width='8')
sfr (key=TMR0 addr=0x1 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR0' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=PCL addr=0x2 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='PCL' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=STATUS addr=0x3 size=1 access='rw rw rw r r rw rw rw')
    reset (por='00011xxx' mclr='000qquuu')
    bit (names='IRP RP nTO nPD Z DC C' width='1 2 1 1 1 1 1')
sfr (key=FSR addr=0x4 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='FSR' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=rw)
sfr (key=PORTA addr=0x5 size=1 access='u u rw rw r rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RA5 RA4 RA3 RA2 RA1 RA0')
    bit (tag=scl names='RA' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=PORTC addr=0x7 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--xxxxxx' mclr='--uuuuuu')
    bit (names='- - RC5 RC4 RC3 RC2 RC1 RC0')
    bit (tag=scl names='RC' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=PCLATH addr=0xA size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---00000')
    bit (names='- - - PCLATH' width='1 1 1 5')
    stimulus (scl=rwb type=int regfiles=w pcfiles=rw)
sfr (key=INTCON addr=0xB size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='0000000u')
    bit (names='GIE PEIE TMR0IE INTE RAIE TMR0IF INTF RAIF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PIR1 addr=0xC size=1 access='rw rw r rw rw rw u rw')
    reset (por='000000-0' mclr='000000-0')
    bit (names='EEIF LVDIF CRIF C2IF C1IF OSFIF - TMR1IF')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=TMR1 addr=0xE size=2 flags=j)
# The j flag means all these registers together form one larger register
    bit (names='TMR1' width='16')
    stimulus (scl=rwb type=int regfiles=w)
sfr (key=TMR1L addr=0xE size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1L' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=TMR1H addr=0xF size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='xxxxxxxx' mclr='uuuuuuuu')
    bit (names='TMR1H' width='8')
    stimulus (scl=rwb type=int regfiles=w pcfiles=w)
sfr (key=T1CON addr=0x10 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='uuuuuuuu')
    bit (names='T1GINV TMR1GE T1CKPS T1OSCEN nT1SYNC TMR1CS TMR1ON' width='1 1 2 1 1 1 1')
    stimulus (scl=rwb regfiles=w)

sfr (key=WDTCON addr=0x18 size=1 access='u u u rw rw rw rw rw')
    reset (por='---01000' mclr='---01000')
    bit (names='- - - WDTPS SWDTEN' width='1 1 1 4 1')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=CMCON0 addr=0x19 size=1 access='r r rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='C2OUT C1OUT C2INV C1INV CIS CM' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=CMCON1 addr=0x1A size=1 access='u u u u u u rw rw')
    reset (por='------10' mclr='------10')
    bit (names='- - - - - - T1GSS C2SYNC')
    stimulus (scl=rwb regfiles=w)

sfr (key=OPTION_REG addr=0x81 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='11111111' mclr='11111111')
    bit (names='nRAPUD INTEDG T0CS T0SE PSA PS' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w)
sfr (key=TRISA addr=0x85 size=1 access='u u rw rw r rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0')
    bit (tag=scl names='TRISA' width='8')
    stimulus (scl=rwb regfiles=w)    
sfr (key=TRISC addr=0x87 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--111111' mclr='--111111')
    bit (names='- - TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0')
    bit (tag=scl names='TRISC' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=PIE1 addr=0x8C size=1 access='rw rw rw rw rw rw u rw')
    reset (por='000000-0' mclr='000000-0')
    bit (names='EEIE LVDIE CRIE C2IE C1IE OSFIE - TMR1IE')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=PCON addr=0x8E size=1 access='u u rw rw rw u rw rw')
    reset (por='--010-qq' mclr='--0u0-uu')
    bit (names='- - ULPWUE SBOREN nWUR - nPOR nBOR')
    stimulus (scl=rwb regfiles=w)
sfr (key=OSCCON addr=0x8F size=1 access='u rw rw rw r r r rw')
    reset (por='-110x000' mclr='-110x000')
    bit (names='- IOSCF OSTS HTS LTS SCS' width='1 3 1 1 1 1')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=OSCTUNE addr=0x90 size=1 access='u u u rw rw rw rw rw')
    reset (por='---00000' mclr='---uuuuu')
    bit (names='- - - TUN' width='1 1 1 5')
    stimulus (scl=rwb regfiles=w pcfiles=rw)

sfr (key=LVDCON addr=0x94 size=1 access='u u r rw u rw rw rw')
    reset (por='--00-000' mclr='--00-000')
    bit (names='- - IRVST LVDEN - LVDL' width='1 1 1 1 1 3')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=WPUDA addr=0x95 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - WPUDA5 WPUDA4 - WPUDA2 WPUDA1 WPUDA0')
    stimulus (scl=rwb regfiles=w)
sfr (key=IOCA addr=0x96 size=1 access='u u rw rw rw rw rw rw')
    reset (por='--000000' mclr='--000000')
    bit (names='- - IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0')
    stimulus (scl=rwb regfiles=w)
sfr (key=WDA addr=0x97 size=1 access='u u rw rw u rw rw rw')
    reset (por='--11-111' mclr='--11-111')
    bit (names='- - WDA5 WDA4 - WDA2 WDA1 WDA0')
    stimulus (scl=rwb regfiles=w)

sfr (key=VRCON addr=0x99 size=1 access='rw u rw u rw rw rw rw')
    reset (por='0-0-0000' mclr='0-0-0000')
    bit (names='VREN - VRR - VR' width='1 1 1 1 4')
    stimulus (scl=rwb regfiles=w)
sfr (key=EEDAT addr=0x9A size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEDAT' width='8')
    stimulus (scl=rwb regfiles=rw pcfiles=rw)
sfr (key=EEADR addr=0x9B size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='EEADR' width='8')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=EECON1 addr=0x9C size=1 access='u u u u rw rw rs rs')
    reset (por='----x000' mclr='----q000')
    bit (names='- - - - WRERR WREN WR RD')
    stimulus (scl=rwb regfiles=w pcfiles=rw)
sfr (key=EECON2 addr=0x9D size=1 flags=w access='w w w w w w w w')
    reset (por='--------' mclr='--------')
    bit (names='EECON2' width='8')

sfr (key=CRCON addr=0x110 size=1 access='rs rw u u u u rw rw')
    reset (por='00----00' mclr='00----00')
    bit (names='GO/nDONE ENC/nDEC - - - - CRREG' width='1 1 1 1 1 1 2')
    bit (tag=scl names='GO_nDONE ENC_nDEC - - - - CRREG' width='1 1 1 1 1 1 2')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT0 addr=0x111 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT0' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT1 addr=0x112 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT1' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT2 addr=0x113 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT2' width='8')
    stimulus (scl=rwb regfiles=w)
sfr (key=CRDAT3 addr=0x114 size=1 access='rw rw rw rw rw rw rw rw')
    reset (por='00000000' mclr='00000000')
    bit (names='CRDAT3' width='8')
    stimulus (scl=rwb regfiles=w)

                               # -------------------#
#------------------------------# Configuration Bits #------------------------------------#
                               # -------------------#

cfgbits (key=CONFIG addr=0x2007 unused=0x2000)
#    illegal (mask=0x48 value=0x48 msg="Current settings of PWRT and BOD are in conflict")
    field (key=OSC mask=0x7 desc="Oscillator")
        setting (req=0x7 value=0x7 desc="External RC Clockout")
        setting (req=0x7 value=0x6 desc="External RC No Clock")
        setting (req=0x7 value=0x5 desc="Internal RC Clockout")
        setting (req=0x7 value=0x4 desc="Internal RC No Clock")
        setting (req=0x7 value=0x3 desc="EC")
        setting (req=0x7 value=0x2 desc="HS")
        setting (req=0x7 value=0x1 desc="XT")
        setting (req=0x7 value=0x0 desc="LP")
    field (key=WDT mask=0x8 desc="Watchdog Timer" min=1)
        setting (req=0x8 value=0x8 desc="On")
        setting (req=0x8 value=0x0 desc="Off")
    field (key=PUT mask=0x10 desc="Power Up Timer")
        setting (req=0x10 value=0x10 desc="Off")
        setting (req=0x10 value=0x0 desc="On")
    field (key=MCLRE mask=0x20 desc="Master Clear Enable")
        setting (req=0x20 value=0x20 desc="External")
        setting (req=0x20 value=0x00 desc="Internal")
    field (key=CP mask=0x40 desc="Code Protect")
        setting (req=0x40 value=0x40 desc="Off")
            checksum (type=0x0 protregion=0x00-0x00)
        setting (req=0x40 value=0x00 desc="On")
            checksum (type=0x20 protregion=0x000-0x7FF)
    field (key=CPD mask=0x80 desc="Data EE Read Protect")
        setting (req=0x80 value=0x80 desc="Off")
        setting (req=0x80 value=0x0 desc="On")
    field (key=BODEN mask=0x300 desc="Brown Out Detect")
        setting (req=0x300 value=0x300 desc="BOD Enabled, SBOREN Disabled")
        setting (req=0x300 value=0x200 desc="BOD enabled in run, disabled in sleep, SBOREN disabled")
        setting (req=0x300 value=0x100 desc="SBOREN controls BOR function")
        setting (req=0x300 value=0x000 desc="BOD and SBOREN disabled")
    field (key=IESO mask=0x400 desc="Internal External Switch Over Mode")
        setting (req=0x400 value=0x400 desc="Enabled")
        setting (req=0x400 value=0x0 desc="Disabled")
    field (key=FCMEN mask=0x800 desc="Monitor Clock Fail-safe")
        setting (req=0x800 value=0x800 desc="Enabled")
        setting (req=0x800 value=0x0 desc="Disabled")
    field (key=WUR mask=0x1000 desc="Wake-Up Reset")
        setting (req=0x1000 value=0x1000 desc="Disabled")
        setting (req=0x1000 value=0x0 desc="Enabled")
                               #-------------#
#------------------------------# Peripherals #------------------------------------#
                               #-------------#

#--------------------------------------------------------------------------------
# 				PORTA
#--------------------------------------------------------------------------------
peripheral (key=PORTA sfrs='TRISA PORTA IOCA' type=port)
    iopin (key=RA0 dir=inout)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN0)
        cnpin (key=C1INP notify=CM)
    iopin (key=RA1 dir=inout)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN1)
        cnpin (key=C1INN notify=CM)
    iopin (key=RA2 dir=inout)
        extint (key=INT0 enreg=INTCON enmask=0x10 flgreg=INTCON flgmask=0x02 prireg=NONE primask=0x00)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN2)
    iopin (key=RA3 dir=inout)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN3)
    iopin (key=RA4 dir=inout)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN4)
        cnpin (key=T1G notify=TMR1)        
    iopin (key=RA5 dir=inout)
        cnint (key=PORTIRQ enreg=INTCON enmask=0x08 flgreg=INTCON flgmask=0x01 prireg=NONE primask=0x00 cnkey=IOCPIN5)

#--------------------------------------------------------------------------------
# 				PORTC
#--------------------------------------------------------------------------------

peripheral (key=PORTC sfrs='TRISC PORTC' type=port)
    iopin (key=RC0 dir=inout)
        cnpin (key=C2INP notify=CM)
    iopin (key=RC1 dir=inout)
        cnpin (key=C2INN notify=CM)
    iopin (key=RC2 dir=inout)
    iopin (key=RC3 dir=inout)
    iopin (key=RC4 dir=inout)
    iopin (key=RC5 dir=inout)


#--------------------------------------------------------------------------------
# 				TIMERs
#--------------------------------------------------------------------------------
peripheral (key=TMR0 sfrs='TMR0')
    pinfunc (key=T0CKI port=RA2 dir=in)
    interrupt (name=TMR0INT enreg=INTCON enmask=0x20 flgreg=INTCON flgmask=0x04 prireg=NONE primask=0x00)

peripheral (key=TMR1 sfrs='TMR1H TMR1L T1CON')
    pinfunc (key=T1CKI port=RA5 dir=in)
    pinfunc (key=T1G port=RA4 dir=in)
    interrupt (name=TMR1INT enreg=PIE1 enmask=0x01 flgreg=PIR1 flgmask=0x01 prireg=NONE primask=0x00)

#--------------------------------------------------------------------------------
# 				CM
#--------------------------------------------------------------------------------

peripheral (key=CM sfrs='CMCON0 CMCON1 VRCON')
    pinfunc (key=C1INP port=RA0 dir=in)
    pinfunc (key=C1INN port=RA1 dir=in)
    pinfunc (key=C1OUT port=RA2 dir=inout)
    pinfunc (key=C2INP port=RC0 dir=in)
    pinfunc (key=C2INN port=RC1 dir=in)
    pinfunc (key=C2OUT port=RC4 dir=inout)
    interrupt (name=CMINT enreg=PIE1 enmask=0x08 flgreg=PIR1 flgmask=0x08 prireg=NONE primask=0x00)
    interrupt (name=CM2INT enreg=PIE1 enmask=0x10 flgreg=PIR1 flgmask=0x10 prireg=NONE primask=0x00)

#--------------------------------------------------------------------------------
# 				KEELOQ
#--------------------------------------------------------------------------------

peripheral (key=KLQ sfrs='CRCON CRDAT0 CRDAT1 CRDAT2 CRDAT3')
    interrupt (name=KLQINT enreg=PIE1 enmask=0x20 flgreg=PIR1 flgmask=0x20 prireg=NONE primask=0x00)

#--------------------------------------------------------------------------------
# 				OSC
#--------------------------------------------------------------------------------

peripheral (key=OSC sfrs='OSCCON')
    pinfunc (key=OSC2 port=RA4 dir=out)
        nextp (nextperiph=TMR1 nextpin=T1G)
    pinfunc (key=OSC1 port=RA5 dir=in)
        nextp (nextperiph=TMR1 nextpin=T1CKI)

#--------------------------------------------------------------------------------
# 				MCLR
#--------------------------------------------------------------------------------
peripheral (key=MCLR)
    pinfunc (key=MCLR port=RA3 dir=in)


#--------------------------------------------------------------------------------
# 				CORE
#--------------------------------------------------------------------------------
peripheral (key=CORE sfrs='EEDAT EEADR EECON1 EECON2 PCON WDTCON')
    interrupt (name=EEINT enreg=PIE1 enmask=0x80 flgreg=PIR1 flgmask=0x80 prireg=NONE primask=0x00)
